Integrated circuits (ICs) typically include external connections for receiving power supply voltages, control or communication signals from external devices and systems. To accommodate demand for computing devices of increasingly smaller size, the internal circuit density of ICs must also increase. In addition, to accommodate demand for low power-consuming devices, power supply potentials used to operate ICs also continues to decrease.
These two trends increase sensitivity of ICs to the effects of electrostatic discharge. Electrostatic discharge (ESD) refers to the discharge of a short burst of high current that results from a build up of static charge on a package, or on a human handling that an IC package. ESD can destroy the internal circuitry of an IC, and hence is a serious concern. Because ESD is so prevalent, IC designers have attempted to integrate ESD protection mechanisms or circuits into their products.
One solution employs a “snap-back” structure to short an input to ground. This type of structure has two conduction modes. At low (non-ESD) voltages the device operates in normal conduction mode, letting only a low leakage current through. When the device is exposed to a high voltage (ESD) event, it enters a “snap-back” mode and conducts higher current or voltage. Typically, such devices stay in “snap-back” mode until voltage or current drops below a minimum level, whereupon they reenter normal mode. Unfortunately, for very high voltage ESD events, these structures can break down and are thus ineffective at limiting the maximum voltage on the input.
A second type of solution, outlined by W. D. Mack and R. G. Meyer, “New ESD Protection Schemes for BiCMOS Process with Applications to Cellular Radio Design,” IEEE ISCAS Proceedings, May 1992, pp. 2699-2702, employs switching transistors to form a switchable conductive circuit between the circuit voltage supply and ground. These transistors are typically turned off during non-ESD events, but activated during an ESD event to provide a discharge path for an ESD current. Typically, the circuit remains active for a period of time dependent on an RC timing circuit (sometimes employing the resistance of the switching transistors themselves).
One variation on this second type is a multiple time-constant electrostatic discharge (ESD) protection scheme as described by M. Stockinger, J. Miller, M. Khazhinsky, C. Torres, J. Weldon, B. Preble and M. Akers, “Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies,” IOS/ESD Symposium Proceedings, 2003. This variation fails to protect against slow ESD events. The circuit shown in FIG. 6 of Stockinger includes a dual-time-constant rail clamp architecture where the time constant R2C2 is set to force the on-time of the clamp to about one microsecond. After the on-time has passed, the clamp turns off, leaving no protection against longer-lasting ESD events. Since in practice ESD events can last tens of microseconds, a one microsecond on-time is insufficient to provide full protection against real world ESD. The naïve solution of simply extending the on-time of the clamp of FIG. 6 by increasing the R2C2 time constant to several tens of microseconds would create another problem by allowing the high-current ESD clamp to stay on for an excessive period of time during normal power-up of the circuit. Since the high current clamp draws high current while it is on, running it for several tens of microseconds during each normal power up would decrease efficiency of the circuit. In fact, the scheme in FIG. 6 of Stockinger includes features designed to prevent even short-time (one microsecond) turn on of the clamp during slower events such as normal power-up. A second time constant, set by the product RC, which is typically in the nanosecond range, provides this functionality. However this feature prevents the whole clamp from protecting against slower ESD events.
These types of RC-timed triggered circuits are effective against certain types of ESD events, e.g. fast, high powered ones, but cannot protect against ESD events of more than a few microseconds in duration, or those that include both fast, high powered transients and also slow acting ones. A clamp that provides ESD protection against both fast and slow transients will enhance manufacturing yields and could be a major advantage in the market, as customers demand increasing levels of protection.